1. Field of the Invention
The present invention relates to electronic packages, and more particularly, to an electronic package having a reduced size and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of miniaturization and high speed. Particularly, communication technologies are integrated in various kinds of electronic products such as cell phones and laptops.
To improve the performance and capacity of single semiconductor packages so as to meet the miniaturization requirement, multichip modules have been widely applied. That is, two or more chips are integrated in a single package so as to reduce the volume of the overall circuit structure and improve the electrical performance.
FIG. 1 is a schematic perspective view of a conventional semiconductor package 1. Referring to FIG. 1, the semiconductor package 1 has a substrate 10, a plurality of semiconductor chips 11 and passive elements 12 disposed on a surface of the substrate 10, and an encapsulant (not shown) encapsulating the semiconductor chips 11 and the passive elements 12.
However, in the conventional semiconductor package 1, the semiconductor chips 11 and the passive elements 12 occupy a large surface area of the substrate 10, thus increasing the volume of the semiconductor package 1 and hindering miniaturization of the semiconductor package 1.
Therefore, how to overcome the above-described drawbacks has become critical.